Computer Science – 15.1 Processors, Parallel Processing and Virtual Machines | e-Consult

Pipelining is a technique used in CPU design to improve performance by overlapping the execution of multiple instructions. It's analogous to an assembly line, where different stages of instruction execution are performed concurrently.

A typical pipeline consists of several stages, such as:

• Instruction Fetch (IF): The instruction is fetched from memory.
• Instruction Decode (ID): The instruction is decoded, and operands are read from the register file.
• Execute (EX): The instruction is executed (e.g., arithmetic operation).
• Memory Access (MEM): If the instruction involves memory access (e.g., load or store), the data is read from or written to memory.
• Write Back (WB): The result of the execution is written back to the register file.

Hazards in Pipelined Execution:

• Data Hazards: An instruction depends on the result of a previous instruction that is still in the pipeline. (e.g., Read After Write (RAW), Write After Read (WAR), Write After Write (WAW)).
• Control Hazards: A branch instruction changes the flow of control, potentially invalidating instructions that have already been fetched.
• Structural Hazards: Two instructions require the same hardware resource at the same time.

Hazard Mitigation Techniques:

• Data Hazards:

  • Forwarding (Bypassing): The result of an instruction is forwarded directly to a subsequent instruction without waiting for it to be written back to the register file.
  • Stalling (Inserting Bubbles): Inserting empty clock cycles (bubbles) into the pipeline to allow the hazard to be resolved.

• Control Hazards:

  • Branch Prediction: Predicting whether a branch will be taken and fetching instructions accordingly.
  • Delayed Branching: Executing instructions after a branch instruction, regardless of whether the branch is taken.

• Structural Hazards:

  • Resource Duplication: Providing duplicate hardware resources to avoid conflicts.